A Survey of Power Management in Embedded System Using Transistor Sizing

This paper describes a transistor sizing methodology for both analog and digital CMOS circuits. Various techniques are used for power optimization in CMOS VLSI circuits. Transistor sizing is one of the important techniques for the determination of circuit performance. The aim of the power optimization is to minimize the power and power-delay product or the energy consumption of the circuit. Thus, the main purpose of transistor sizing in CMOS VLSI circuits is to obtain the minimum power dissipation under certain performance requirements. Transistor sizing is based on different algorithms. Analysis is based on some simulation parameter like No. of transistors, power, delay, power delay product, different technologies, aspect ratio. Each of these circuits cell exhibits different power consumption, delay and area in different VLSI technology. This survey paper discusses the different algorithms for transistor sizing analog and digital CMOS circuits and that will be beneficial for the circuit designers. Key-Words: Algorithm, Delay, Low Power, Optimization, Transistor sizing.